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nexflash technologies, inc. 1 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? preliminary april 2005 1m-bit, 2m-bit and 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40
2 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table of contents nx25p10, NX25P20 and nx25p40 1m-bit, 2m-bit and 4m-bit serial flash memory with 40mhz spi ................................................................... ........ 1 features ............................................................................................................................... ...................................... 4 general description ............................................................................................................................... .............. 4 8-pin soic 150-mil (package code n) .......... .................................................................................. .............................. 4 figure 1. nx25p10, NX25P20 and nx25p40 block diagram ........................................................................... ......... 5 pin descri ptions ............................................................................................................... ....................................... 6 package types .................................................................................................................. ....................................... 6 serial data input (di) ......................................................................................................... ....................................... 6 serial data output (do) ........................................................................................................ .................................... 6 serial clock (c lk) ............................................................................................................. ....................................... 6 chip select (c s) ............................................................................................................... ........................................ 6 hold (hold) ............................................................................................................................... .............................. 6 write protect (w p) ............................................................................................................. ....................................... 6 figure 2. nx25p10, NX25P20 and nx25p40 pin assignments, 8-pin soic (package code n) ................................ 6 table 1. pin descr iptions ...................................................................................................... .................................... 6 spi opera tion .................................................................................................................. .......................................... 7 spi modes ...................................................................................................................... ......................................... 7 hold function ............................................................................................................................... ............................ 7 write protection ............................................................................................................................... ..................... 7 write protect features ......................................................................................................... ..................................... 7 status register ................................................................................................................ ....................................... 8 busy ........................................................................................................................... ............................................ 8 write enable latch (wel) ....................................................................................................... .................................. 8 figure 3. status register bit locations ........................................................................................ ............................. 8 block protect bits (bp2, bp1, bp0) ............................................................................................. ............................ 8 reserved bits .................................................................................................................. ......................................... 8 status register protect (srp) .................................................................................................. ................................ 8 table 2: status register memory protection ..................................................................................... ........................ 9 instructions ............................................................................................................................... ............................ 10 table 3: instruction set ....................................................................................................... .................................... 10 table 4: manuf acturer and de vice identification ................................................................................ ...................... 10 write enable (06h) ............................................................................................................. ....................................... 11 figure 4. write enable instruction sequence diag ram ............................................................................ ................. 11 write disable (04h) ............................................................................................................................... .................... 11 figure 5. write disable inst ruction sequence diagra m ........................................................................... ................. 11 read status register (05h) ............................................................................................................................... ....... 12 figure 6. read status register instruction sequen ce diag ram .................................................................... ........... 12 write status register (01h) ............................................................................................................................... ....... 13 figure 7. write status register instruction sequence diag ram ................................................................... ............ 13 read data (03h) ............................................................................................................................... ......................... 14 figure 8. read data instruction sequence diagram ............................................................................... ................. 14
nexflash technologies, inc. 3 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table of contents fast read (0bh) ............................................................................................................................... ......................... 15 figure 9. fast read instr uction sequence diag ram ............................................................................... ................. 15 page prog ram (02h ) ............................................................................................................. .................................... 16 figure 10. page program instruction sequence diag ram ........................................................................... ............. 16 sector erase (d8h) ............................................................................................................................... .................... 17 figure 11. sector erase instruction sequence diagram ........................................................................... ............... 17 bulk erase (c7h) ............................................................................................................................... ....................... 18 figure 12. bulk erase instruction sequence diagram ............................................................................. ................ 18 power-down (b9h) ............................................................................................................................... ..................... 19 figure 13. deep power-down instruction sequence diagram ................................................................................... 19 release power-down / device id (abh) ........................................................................................... ........................ 20 figure 14. release power-do wn instruction sequence ............................................................................. ............... 20 figure 15. release power-down / devi ce id instr uction sequence diag ram ......................................................... ... 20 read manufacturer / device id (90h) ............................................................................................ ........................... 21 figure 16. read manufacturer / device id diagram ............................................................................... ................. 21 specifications and timing diagrams ............................................................................................................... 22 table 5. absolute maximum ratings .............................................................................................. ......................... 22 table 6. operating ranges ...................................................................................................... ................................ 22 table 7. power-up timing and wr ite inhibit threshol d ........................................................................... ................... 22 figure 17. power-up timing and voltage le vels .................................................................................. ..................... 22 table 8. dc electrical characteristics (preliminary) ........................................................................... ..................... 23 table 9. ac measurement conditions ............................................................................................. ........................ 23 figure 18. ac measurement i/o waveform ......................................................................................... .................... 23 table 10. ac elect rical character istics (preliminar y) .......................................................................... ..................... 24 figure 19. ser ial output timing ................................................................................................ ............................... 25 figure 20. input timing ........................................................................................................ ................................... 25 figure 21. hold timing ......................................................................................................... ................................... 25 packaging information ............................................................................................................................... ......... 26 8-pin soic 150-mil (package code n) ............................................................................................ ........................... 26 preliminary designation ............................................................................................................................... ..... 27 important notice ............................................................................................................................... .................... 27 ordering information ............................................................................................................................... .......... 27 life support policy ............................................................................................................ ................................. 27 trademarks ............................................................................................................................... .............................. 27 document revision history ............................................................................................................................... ......... 28
4 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 general description the nx25p10 (1m-bit), NX25P20 (2m-bit) and nx25p40 (4m-bit) serial flash memories provide a storage solution for systems with limited space, pins and power. they are ideal for code download applications as well as storing voice, text and data. the devices operate on a single 2.7v to 3.6v power supply with current consumption as low as 4ma active and 1a for power-down. all devices are offered in space-saving 8-pin soic type packages as shown below. contact nexflash for availability of alternate pack- ages. as part of a family of serial flash products, nexflash also provides a compatible migration path to 8m/ 16m/32m-bit densities. the nx25p10/20/40 array is organized into 512/1024/2048 programmable pages of 256-bytes each. a single byte or, up to 256 bytes, can be programmed at a time using the page program instruction. pages are grouped into 2/4/8 erasable sectors of 256 pages (64k-byte) each as shown in figure 1. both sector erase and bulk (full chip) erase instructions are supported. the serial peripheral interface (spi) consists of four pins (serial clock, chip select, serial data in and serial data out) that support high speed serial data transfers up to 40mhz. a hold pin, write protect pin and programmable write protect features provide further control flexibility. additionally, the device can be queried for manufacturer and device id. special customer id (for copy authentica- tion) and factory programming is available, contact nex- flash for more information. features ? 1m / 2m / 4m-bit serial flash memories family of serial flash memories ? nx25p10: 1m-bit / 128k -byte (131,072 ) 512 pages ? NX25P20: 2m-bit / 256k -byte ( 262,144 ) 1024 pages ? nx25p40: 4m-bit / 512k -byte ( 524,288 ) 2048 pages ? 256-bytes per programmable page ? compatible migration path to 8m/16m/32m-bit 4-pin spi serial interface ? clock, chip select, data in, data out ? easily interfaces to popular microcontrollers ? compatible with spi modes 0 and 3 ? optional hold function for spi flexibility low power consumption, wide temperature range ? single 2.7 to 3.6v supply ? 4ma active current, 1a power-down (typ) ? -40 to +85c operating range fast and flexible serial data access ? clock operation to 40mhz fast read, 33mhz standard read ? byte-addressable read and program ? auto-increment read capability ? manufacturer and device id programming features ? page program up to 256 bytes <2ms ? sector erase (64k-byte) 2 seconds ? chip erase: 3 seconds (25p10/20), 5 seconds (25p40) ? 100,000 erase/write cycles ? twenty year data retention software and hardware write protection ? write-protect all or portion of memory via software ? enable/disable protection with wp pin space saving package ? tiny 8-pin soic ideal for systems with limited pins, space, and power ? asic and controller-based serial code-download ? microcontroller systems storing data, text or voice ? battery-operated and portable products 8-pin soic 150-mil (package code n)
nexflash technologies, inc. 5 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 000000h 0000ffh 07ff00h 07ffffh 070000h 0700ffh 06ff00h 06ffffh 060000h 0600ffh 05ff00h 05ffffh 050000h 0500ffh 04ff00h 04ffffh 040000h 0400ffh 03ff00h 03ffffh 030000h 0300ffh 02ff00h 02ffffh 020000h 0200ffh 01ff00h 01ffffh 010000h 0100ffh 00ff00h 00ffffh serial flash memory array NX25P20 nx25p10 nx25p40 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 * * every sector consists of 256 pages of 256 bytes each write protect logic row decode column decode and 256 byte page buffer high-voltage generators page address latch / counter data write control logic wp h old status register spi comand and control logic byte address latch / counter clk cs di do begining page address ending page address figure 1. nx25p10, NX25P20 and nx25p40 block diagram
6 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table 1. pin descriptions di data input do data output clk serial clock input cs chip select input wp write protect input hold hold input vcc, gnd power supply pin descriptions package types the standard package for the nx25p10/20/40 is an 8-pin plastic soic with 150 mil body (nexflash package code n). it also allows a package migration path to higher density serial flash devices. the pinout for the ?n? package is shown in figure 2. package diagrams and dimensions are illustrated at the end of this data sheet. optional 8-contact mlp packages may be available. please contact nexflash for further mlp package information. serial data input (di) the spi serial data input (di) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. data is latched on the rising edge of the serial clock (clk) input pin. serial data output (do) the spi serial data output (do) pin provides a means for data and status to be serially read from (shifted out of) the device. data is shifted out on the falling edge of the serial clock (clk) input pin. serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. ("see spi "operations") chip select ( cs cs cs cs cs ) the spi chip select ( cs ) pin enables and disables device operation. when cs is high the device is deselected and the serial data output (do) pin is at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. when cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up, cs must transition from high to low before a new instruction will be accepted. the cs input must track the vcc supply level at power-up (see ?write protection? and figure 17). if needed a pull-up resister on cs can be used to accomplish this. hold ( hold hold hold hold hold ) the hold pin allows the device to be paused while it is actively selected. when hold is brought low, while cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (don?t care). when hold is brought high, device operation can resume. the hold function can be useful when multiple devices are sharing the same spi signals. (?see hold function?) cs do wp gnd 1 2 3 4 8 7 6 5 vcc hold clk di figure 2. nx25p10, NX25P20 and nx25p40 pin assignments, 8-pin soic (package code n) write protect ( wp wp wp wp wp ) the write protect ( wp ) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block protect (bp0 and bp1) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. the wp pin is active low.
nexflash technologies, inc. 7 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 spi operation spi modes the nx25p10/20/40 is accessed through an spi compat- ible bus consisting of four signals: serial clock (clk), chip select ( cs ), serial data input (di) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the di pin is sampled on the rising edge of the clk. data output on the do pin is clocked out on the falling edge of clk. hold function the hold signal allows the nx25p10/20/40 operation to be paused while it is actively selected (when cs is low). the hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. to initiate a hold condition, the device must be selected with cs low. a hold condition will activate on the falling edge of the hold signal if the clk signal is already low. if the clk is not already low the hold condition will activate after the next falling edge of clk. the hold condition will terminate on the rising edge of the hold signal if the clk signal is already low. if the clk is not already low the hold condition will terminate after the next falling edge of clk. during a hold condition, the serial data output (do) is high impedance, and serial data input (di) and serial clock (clk) are ignored. the chip select ( cs ) signal should be kept active (low) for the full duration of the hold operation to avoid resetting the internal logic state of the device. write protection applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern the nx25p10/20/40 provides several means to protect data from inadvertent writes. write protect features device resets when vcc is below threshold. time delay write disable after power-up. write enable/disable instructions. automatic write disable after program and erase. software write protection using status register. hardware write protection using status register and wp pin. write protection using power-down instruction. upon power-up or at power-down the nx25p10/20/40 will maintain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels: table 7 and figure 17). while reset, all operations are disabled and no instructions are recognized. during power- up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page pro- gram, sector erase, bulk erase and the write status register instructions. note that the chip select pin ( cs ) must track the vcc supply level at power-up until the vcc- min level and t vsl time delay is reached. if needed a pull-up resister on cs can be used to accomplish this. after power-up the device in automatically placed in a write- disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, bulk erase or write status register in struction w ill be accepted. after complet- ing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write status register instruction and setting the status register protect (srp) and block protect (bp0, bp2) bits. these status register bits allow a portion or all of the memory to be configured as read only. used in conjunction with the write protect ( wp ) pin, changes to the status register can be enabled or disabled under hardware control. see status register for further information. additionally, the power-down instruction offers an extra level of write protection as all instructions are ignored except for the release power-down instruction.
8 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 s7 s6 s5 s4 s3 s2 s1 s0 srp (reserved) bp2 bp1 bp0 wel busy status registerprotect (non-volatile) block protect bits (non-volatile) write enable latch device busy erase program or write in progress figure 3. status register bit locations status register the read status register instruction can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, and the state of write protection. the write status register instruction can be used to configure the devices write protection features. see figure 3. busy busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, sector erase, bulk erase or write status register instruc- tion. during this time the device will ignore further instruc- tions except for the read status register instruction (see t w , t pp , t se and t be in ac characteristics). when the program, erase or write status register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing a write enable instruction. the wel status bit is cleared to a 0 when the device is write disabled. a write disable state occurs upon power-up or after any of the following instructions: write disable, page program, sector erase, bulk erase and write status register. block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0) are non-volatile read/write bits in the status register (s4, s3, s2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see tw in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see table 2). the factory default setting for the block protection bits is 0, none of the array protected. the block protect bits can not be written to if the status register protect (srp) bit is set to 1 and the write protect ( wp ) pin is low. the NX25P20 and nx25p10 do not use bp2. reserved bits status register bit locations 5 and 6 are reserved for future use. current devices will read 0 for these bit locations. it is recommended to mask out the reserved bit when testing the status register. doing this will ensure compatibility with future devices. status register protect (srp) the status register protect (srp) bit is a non-volatile read/ write bit in the status register (s7) that can be used in conjunction with the write protect ( wp ) pin to disable writes to the status register. when the srp bit is set to a 0 state (factory default) the wp pin has no control over the status register. when the srp pin is set to a 1, the write status register instruction is locked out while the wp pin is low. when the wp pin is high the write status register instruc- tion is allowed.
nexflash technologies, inc. 9 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table 2: status register memory protection status register (1) nx25p40 (4m-bit) memory protection bp2 bp1 bp0 sector(s) addresses d ensity portion 0 0 0 none none none none 0 0 1 7 070000h - 07ffffh 512k-bit u pper 1/8 0 1 0 6 and 7 060000h - 07ffffh 1m-bit u pper 1/4 0 1 1 4 thru 7 040000h - 07ffffh 2m-bit u pper 1/2 1 x x all 000000h - 07ffffh 4m-bit all status register (1) NX25P20 (2m-bit) memory protection bp2 bp1 bp0 sector(s) addresses d ensity portion x 0 0 none none none none x 0 1 3 030000h - 03ffffh 512k-bit u pper 1/4 x 1 0 2 and 3 020000h - 03ffffh 1m-bit u pper 1/2 x 1 1 all 000000h - 03ffffh 2m-bit all status register (1) nx25p10 (1m-bit) memory protection bp2 bp1 bp0 sector(s) addresses d ensity portion x 0 x none none none none x 1 0 none none none none x 1 1 all 000000h - 01ffffh 1m-bit all notes: 1. x = don't care.
10 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table 3: instruction set (1) instruction name byte 1 byte 2 (5) byte 3 byte 4 byte 5 byte 6 n- bytes code write enable 06h write disable 04h read status register 05h (s7?s0) (1) (2) write status register 01h s7?s0 read data 03h a23?a16 a15?a8 a7?a0 (d7 ?d0) (next byte) continuous fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7 ?d0) (next byte) continuous page program 02h a23?a16 a15?a8 a7?a0 (d7 ?d0) (next byte) up to 256 bytes sector erase d8h a23?a16 a15?a8 a7?a0 (6) bulk erase c7h power-down b9h release power-down abh dummy dummy dummy (id7-id0) (3) and device id manufacturer/device id 90h dummy dummy 00h (m7-m0) (id7-id0) (4) notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ?( )? indicate data being read f rom the device on the do pin. 2. the status register contents will repeat continuously until cs terminate the instruction. 3. the device id will repeat continuously until cs terminate the instruction. 4. the manufacturer id and device id bytes will repeat continuously until cs terminate the instruction. 5. unused upper address bits must be set to a 0 for the nx25p10. 6. the lowest 16 address bits (a15-a0) must be set to 0. table 4: manufacturer and device identification manufacturer id (m7-m0) nexflash efh device id (id7-id0) nx25p10 10h NX25P20 11h nx25p40 12h instructions the instruction set of the nx25p10/20/40 consists of twelve basic instructions that are fully controlled through the spi bus (see table 3). instructions are initiated with the falling edge of chip select ( cs ). the first byte of data clocked into the di input provides the instruction code. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don?t care), and in some cases, a combina- tion. instructions are completed with the rising edge of edge cs . clock relative timing diagrams for each instruction are included in figures 5 through 17. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary ( cs driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructions except for read status register will be ignored until the program or erase cycle has completed.
nexflash technologies, inc. 11 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 instruction (06h) high impedance mode 0 mode 3 cs clk di do figure 4. write enable instruction sequence diagram 0 1 2 3 4 5 6 7 instruction (04h) high impedance mode 0 mode 3 cs clk di do figure 5. write disable instruction sequence diagram write enable (06h) the write enable instruction (figure 4) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, sector erase, bulk erase and write status register instruction. the write enable instruction is entered by driving cs low, shifting the instruction code ?06h? into the data input (di) pin on the rising edge of clk, and then driving cs high. write disable (04h) the write disable instruction (figure 5) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving cs low, shifting the instruction code ?04h? into the di pin and then driving cs high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, page program, sector erase, and bulk erase instructions.
12 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 instruction (05h) high impedance 7 status register out status register out mode 0 mode 3 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * * = msb cs clk di do figure 6. read status register instruction sequence diagram read status register (05h) the read status register instruction allows the 8-bit status register to be read. the instruction is entered by driving cs low and shifting the instruction code ?05h? into the di pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 6. the status register bits are shown in figure 3 and include the busy, wel, bpo-bp2, and stp bits (see description of the status register earlier in this data sheet). the status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the status register can be read continuously, as shown in figure 6. the instruction is completed by driving cs high.
nexflash technologies, inc. 13 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction (01h) high impedance status register in mode 0 mode 3 7 6 5 4 3 2 1 0 * = msb * cs clk di do figure 7. write status register instruction sequence diagram write status register (01h) the write status register instruction allows the status register to be written. a write enable instruction must previously have been executed for the device to accept the write status register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving cs low, sending the instruction code ?01h?, and then writing the status register data byte as illustrated in figure 7. the status register bits are shown in figure 3 and described earlier in this data sheet. for the nx25p40, only non-volatile status register bits stp, bp2, bp1 and bp0 (bits 7, 4, 3 and 2) can be written to. for the NX25P20 and nx25p10 only status register bits stp, bp1 and bp0 (bits 7, 3 and 2) can be written to. all other status register bit locations are read-only and will not be affected by the write status register instruction. the cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the write status register instruction will not be executed. after cs is driven high, the self-timed write status register cycle will com- mence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status register instruction may still accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write register cycle has started the write enable latch (wel) bit in the status register will be cleared to 0. the write status register instruction allows the block protect bits (bp2, bp1 and bp0) to be set for protecting all, a portion, or none of the memory from erase and program instructions. protected areas become read-only (see table 2). the write status register instruction also allows the status register protect bit (srp) to be set. this bit is used in conjunction with the write protect ( wp ) pin to disable writes to the status register. when the srp bit is set to a 0 state (factory default) the wp pin has no control over the status register. when the srp pin is set to a 1, the write status register instruction is locked out while the wp pin is low. when the wp pin is high the write status register instruction is allowed.
14 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 instruction (03h) high impedance 24-bit addess data out 1 data out 2 33 34 35 36 37 38 39 7 23 22 21 3 2 1 0 mode 0 mode 3 * * * = msb 7 6 5 4 3 2 1 0 cs clk di do figure 8. read data instruction sequence diagram read data (03h) the read data instruction allows one or more data bytes to be sequentially read from the memory. the instruction is initiated by driving the cs pin low and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving cs high. the read data instruction sequence is shown in figure 8. if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r ( see ac electrical characteristics).
nexflash technologies, inc. 15 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 instruction (0bh) mode 0 mode 3 24-bit address 23 22 21 3 2 1 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 dummy byte data out 1 data out 2 7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 *** * = msb cs clk di do cs clk di do figure 9. fast read instruction sequence diagram fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding a ?dummy? byte after the 24-bit address as shown in figure 9. the dummy byte allows the devices internal circuits additional time for setting up the initial address. the dummy byte data value on the di pin is a ?don?t care?.
16 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 ** 0 1 2 3 4 5 6 7 8 9 10 instruction (02h) mode 0 mode 3 24-bit address data byte 1 23 22 21 3 2 1 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 data byte 2 data byte 3 data byte 256 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 28 29 30 31 32 33 34 35 36 37 38 39 * = msb ** * cs clk di cs clk di 2072 2073 2074 2075 2076 2077 2078 2079 figure 10. page program instruction sequence diagram page program (02h) the page program instruction allows from one byte to 256 bytes of data to be programmed at memory locations previously erased to all 1s (ffh). a write enable instruction must be executed before the device will accept the page program instruction (status register bit wel must equal 1). the instruction is initiated by driving the cs pin low then shifting the instruction code ?02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the di pin. the cs pin must be driven low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 10. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. less than 256 bytes can be programmed without having any effect on other bytes within the same page. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after cs is driven high, the self-timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has started the write enable latch (wel) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, bp0) bits (see table 2).
nexflash technologies, inc. 17 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 8 9 29 30 31 instruction (d8h) high impedance mode 0 mode 3 24-bit address 23 22 2 1 0 cs clk di do * * = msb figure 11. sector erase instruction sequence diagram sector erase (d8h) the sector erase instruction sets all memory within a specified sector to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the erase sector instruction (status register bit wel must equal 1). the instruction is initiated by driving the cs pin low and shifting the instruction code ?d8h? followed a 24-bit sector address (a23-a0) (see figure 1). the lowest 16 address bits (a15-a0) must be set to 0. the sector erase instruction sequence is shown in figure 11. the cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after cs is driven high, the self-timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruc- tion may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has started the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, bp0) bits (see table 2).
18 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 instruction (c7h) high impedance mode 0 mode 3 cs clk di do figure 12. bulk erase instruction sequence diagram bulk erase (c7h) the bulk erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the bulk erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the cs pin low and shifting the instruction code ?c7h?. the bulk erase instruction sequence is shown in figure 12. the cs pin must be driven high after the eighth bit has been latched. if this is not done the bulk erase instruction will not be executed. after cs is driven high, the self-timed bulk erase instruction will commence for a time duration of t be (see ac characteristics). while the bulk erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the bulk erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the bulk erase cycle has started the write enable latch (wel) bit in the status register is cleared to 0. the bulk erase instruction will not be executed if any page is protected by the block protect (bp2, bp1, bp0) bits (see table 2).
nexflash technologies, inc. 19 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 instruction (b9h) t dp high impedance stand-by current power-down current mode 0 mode 3 cs clk di do figure 13. deep power-down instruction sequence diagram power-down (b9h) although the standby current during normal operation is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the cs pin low and shifting the instruction code ?b9h? as shown in figure 13. the cs pin must be driven high after the eighth bit has been latched. if this is not done the power-down instruction will not be executed. after cs is driven high, the power-down state will entered within the time duration of t dp (see ac characteristics). while in the power-down state only the release from power-down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with the standby current of icc1.
20 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 instruction (abh) t res1 high impedance power-down current stand-by current mode 0 mode 3 cs clk di do figure 14. release power-down instruction sequence 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 instruction (abh) 3 dummy bytes t res2 high impedance stand-by current power-down current device id ** mode 0 mode 3 cs clk di do 7 6 5 4 3 2 1 0 * = msb ** = see table 4 * 23 22 21 3 2 1 0 * figure 15. release power-down / device id instruction sequence diagram release power-down / device id (abh) the release from power-down / device id instruction is a multi-purpose instruction. it can be used to release the device from the power-down state, obtain the devices electronic identification (id) number or do both. when used only to release the device from the power-down state, the instruction is issued by driving the cs pin low, shifting the instruction code ?abh? and driving cs high as shown in figure 14. after the time duration of t res 1 (see ac characteristics) the device will resume normal operation and other instructions will be accepted. the cs pin must remain high during the t res 1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the cs pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 15. the device id values for the nx25p10, NX25P20, and nx25p40 are listed in table 4. the device id can be read continuously. the instruction is completed by driving cs high. when used to release the device from the power-down state and obtain the device id, the instruction is the same as previously described, and shown in figure 13, except that after cs is driven high it must remain high for a time duration of t res 2 (see ac characteristics). after this time duration the device will resume normal operation and other instruc- tions will be accepted. if the release from power-down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle.
nexflash technologies, inc. 21 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 instruction (90h) address (000000h) high impedance mode 0 mode 3 cs clk di do * = msb ** = see table 4 23 22 21 3 2 1 0 * 32 33 34 35 36 37 38 39 40 41 42 43 44 45 manufacturer id ( efh ) device id ( ** ) cs clk di do 7 6 5 4 3 2 1 0 * figure 16. read manufacturer / device id diagram read manufacturer / device id (90h) the read manufacturer/device id instruction is an alterna- tive to the release from power-down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving the cs pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufac- turer id for nexflash (efh) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 16. the device id values for the nx25p10, NX25P20, and nx25p40 are listed in table 4. if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is com- pleted by driving cs high.
22 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table 5. absolute maximum ratings (1) symbol par ameters conditions range unit vcc supply voltage ?0.6 to +4.0 v v io voltage applied to any pin relative to ground ?0.6 to vcc + 0.4 v t stg storage temperature ?65 to +150 c t lead lead temperature see note 2 c v esd electrostatic discharge voltage human body model (3) ?2000 to +2000 v note: 1. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure beyond absolute maximum ratings (listed above) may cause permanent damage. 2. compliant with jedec standard j-std-20c for small body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). table 6. operating ranges symbol parameter cond itions min max unit vcc supply voltage (1) f r = 33mhz, f r = 20mhz 2.7 3.6 v f r = 40mhz, f r = 33mhz 3.0 3.6 v t a ambient temperature, operating industrial ?40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage. table 7. power-up timing and write inhibit threshold symbol parameter min max unit t vsl (1) vcc(min) to cs low 10 s t puw (1) time delay before write instruction 1 10 ms v wi (1) write inhibit threshold voltage 1 2 v note: 1. these parameters are characterized only. vcc vcc (max) vcc (min) v wi reset state t puw t vsl read instructions allowed device is fully accessible program, erase and write instructions are ignored cs must track vcc time figure 17. power-up timing and voltage levels specifications and timing diagrams
nexflash technologies, inc. 23 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table 8. dc electrical characteristics (preliminary) (1) symbol parameter cond itions min typ max unit c in (2) input capacitance v in = 0v (2) 6pf cout (2) output capacitance v out = 0v (2) 8pf i li input leakage 2 a i lo i/o leakage 2 a i cc1 standby current cs = vcc, vin = gnd or vcc 25 50 a i cc2 power-down current cs = vcc, vin = gnd or vcc <1 5 a i cc3 current read data 1mhz c = 0.1vcc / 0.9 vcc do = open 4 7 ma current read data 20mhz c = 0.1vcc / 0.9 vcc do = open 10 14 ma current read data 33mhz c = 0.1vcc / 0.9 vcc do = open 14 18 ma i cc4 current page program cs = vcc 15 20 ma i cc5 current write status register cs = vcc 8 20 ma i cc6 current sector erase cs = vcc 15 25 ma i cc7 current bulk erase cs = vcc 17 25 ma v il input low voltage ?0.5 vccx0.3 v v ih input high voltage vccx0.7 vcc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 a v cc ?0.2 v notes: 1. see preliminary designation. 2. tested on sample basis and specified through design and characterization data. ta=25 c, vcc 3v, frequency 20mhz. 0.8 vcc 0.7 vcc 0.3 vcc 0.2 vcc input levels input and output timing reference levels figure 18. ac measurement i/o waveform table 9. ac measurement conditions symbol parameter min max unit c l load capacitance 30 30 pf t r , t f input rise and fall times 5 ns v in input pulse voltages 0.2vcc to 0.8vcc v o ut output timing reference voltages 0.3vcc to 0.7vcc v note: 1. output hi-z is defined as the point where data out is no longer driven.
24 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 table 10. ac electrical characteristics (preliminary) symbol alt description min typ max unit f r f c clock frequency, for fast read (0bh) and all other instructions except read data (03h) 2.7v-3.6v vcc d.c. 33 mhz 3.0v-3.6v vcc d.c. 40 mhz f r clock freq. read data instruction (03h) 2.7v-3.6v vcc d.c. 20 mhz 3.0v-3.6v vcc d.c. 33 mhz t clh , t cll (1) clock high, low time, for fast read (0bh) 11 ns and all other instructions except read data (03h) t crlh , t crll (1) clock high, low time for read data instruction (20 / 33-40mhz) 18 / 11 ns t clch (2) clock rise time peak to peak 0.1 v / ns t chcl (2) clock fall time peak to peak 0.1 v / ns t slch t css cs active setup time relative to clk (20 / 33-40mhz) 10 / 5 ns t chsl cs not active hold time relative to clk (20 / 33-40mhz) 10 / 5 ns t dvch t dsu data in setup time (20 / 33-40mhz) 5 / 2 ns t chdx t dh data in hold time 5 ns t chsh cs active hold time relative to clk (20 / 33-40mhz) 10 / 5 ns t shch cs not active setup time relative to clk (20 / 33-40mhz) 10 / 5 ns t shsl t csh cs deselect time 100 ns t shqz (2) t dis output disable time (20 / 33-40mhz) 15 / 9 ns t clqv t v clock low to output valid (20 / 33-40mhz) 15 / 10 ns t clqx t ho output hold time 0 ns t hlch hold active setup time relative to clk (20 / 33-40mhz) 10 / 5 ns t chhh hold active hold time relative to clk (20 / 33-40mhz) 10 / 5 ns t hhch hold not active setup time relative to clk (20 / 33-40mhz) 10 / 5 ns t chhl hold not active hold time relative to clk (20 / 33-40mhz) 10 / 5 ns t hhqx (2) t lz hold to output low-z (20 / 33-40mhz) 15 / 9 ns t hlqz (2) t hz hold to output high-z (20 / 33-40mhz) 20 / 9 ns t whsl (4) write protect setup time before cs low 20 ns t shwl (4) write protect hold time after cs high 100 ns t dp (2) cs high to power-down mode 3 s t res 1 (2) cs high to standby mode without electronic 3 s signature read t res 2 (2) cs high to standby mode with electronic 1.8 s signature read t w write status register cycle time 10 15 ms t pp page program cycle time 2 5 ms t se sector erase cycle time 0.7 3 s t be bulk erase cycle time 25p10 and 25p20 3 6 s bulk erase cycle time 25p40 5 10 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a write status register instruction when sector protect bit is set at 1.
nexflash technologies, inc. 25 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 cs clk do lsb out di tqlqh tqhql * least significant address bit (lsb) in tclqv tclqx tshqz tcl tch tclqx tclqv * figure 19. serial output timing figure 20. input timing (high impedance) tclch msb in lsb in tchsl tshsl tchcl tdvch tslch tchdx tchsh tshch cs clk di do cs hold clk do di tchhl thlch tchhh thhqx thhch thlqz figure 21. hold timing
26 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 packaging information 8-pin soic 150-mil (package code n) 1 d e1 e a seating plane a1 l c e b cp a2 notes: 1. controlling dimensions: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within .0004 inches at the seating plane. package dimensions (1) millimeters inches symbol min typ. max min typ. max a 1.47 1.60 1.72 0.058 0.063 0.068 a1 0.10 0.24 0.004 0.009 a2 1.45 0.057 b 0.33 0.41 0.50 0.013 0.016 0.020 c 0.19 0.20 0.25 0.0075 0.008 0.0098 d (3) 4.80 4.85 4.95 0.189 0.191 0.195 e 5.80 6.00 6.19 0.228 0.236 0.244 e1 (3) 3.80 3.90 4.00 0.150 0.154 0.157 e (2) 1.27 bsc 0.050 bsc l 0.40 0.71 1.27 0.015 0.028 0.050 0 o 8 o 0 o 8 o cp 0.10 0.004
nexflash technologies, inc. 27 preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1 2 3 4 5 6 7 8 9 10 11 12 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 preliminary designation the ?preliminary? designation on a nexflash data sheet indicates that the product is not fully characterized. the specifications are subject to change and are not g ua ran- teed. nexflash or an authorized sales representative should be consulted for current information before using this product. important notice nexflash reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. nexflash assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary de- pending upon a user?s specific application. while the information in this publication has been carefully checked, nexflash shall not be liable for any damages arising as a result of any error or omission. life support policy nexflash does not recommend the use of any of it's products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure in the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless nexflash receives written assurances, to it?s satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of nexflash is adeq ua tely pro- tected under the circumstances. trademarks nexflash and spiflash are trademarks of nexflash technologies, inc . all other marks are the property of their respective owner. ordering information nx 25p xx - v x i - xx.. company prefix nx = nexflash product family 25p = spiflash serial flash memory product number / density 10 = 1m-bit 20 = 2m-bit 40 = 4m-bit supply voltage v = 2.7v to 3.6v package type n = 8-pin soic 150-mil p = 8-contact mlp 6x5mm * temperature range i = industrial (?40?c to +85?c) special options (blank) standard package g = green package (lead-free, rohs compliant) c = customer specification (for factory programming and other custom specifications ) t = tape and reel * contact nexflash for availability of this package.
28 nexflash technologies, inc. preliminary mkp-0009 rev 6 nxsf040i-0405 04/04/05 ? 1m / 2m / 4m-bit serial flash memory with 40mhz spi nx25p10, NX25P20 and nx25p40 document revision history date rev description of revision 04/29/03 a document written 09/12/03 b incorporated spiflash trademark for nx25p10, 20 and 40 product family. adjusted data for consistency 03/09/04 c adjusted pages 10, 11, 14, 16 and 24 for technical clarity. updated special options and ordering information 03/24/04 d mlp metal die pad notification; under "package types," figure 3 and packaging information. 05/11/04 e corrected dimensions in packaging information section for 6x5mm mlp. updated characterization information dc (table 8) & ac (table 10). 06/16/04 f modified dimensional data in the packaging information for the 6x5mm mlp package 11/23/04 g added fr = 40mhz @ 3.0v to 3.6v vcc. added fr = 33mhz @ 3.0v to 3.6v vcc. modified t lead in absolute maximum ratings (table 5) to reference jedec standard information. added f r and f r conditions to operating ranges (table 6). updated i cc 3 and i cc 5 data in dc electri- cal characteristics (table 8). added 20/33mhz call outs and updated min, max and typ data in ac electrical characteristics (table 10). 12/08/04 h updated 8-pin 150mil soic package information. 04/04/05 i removed 8-contact 6x5 mlp package from document.

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